Design Verification Tools In Vlsi

VLSI DESIGN AND VERIFICATION

Perfection driven design. Paranoia driven verification.

A designer knows he has achieved perfection not when there is nothing left to add but when there is nothing left to take away. At Ignitarium, we strive for minimalism-driven designs, squeezing every ounce of performance while staying within the optimal area and power envelope. These designs are then put through the proverbial wringer by our verification teams, who are armed with system level understanding, advanced verification methodologies and most importantly, rigor and attention to detail.

Do it right with Ignitarium.

Digital Design: Optimum IPs and SoCs

Ignitarium's design strength comes from the possession of a library of design components which could be customized to meet customer requirements, together with the knowhow and skill of its engineering team to harmonize multidimensional and often competing design requirements to optimum implementations. We pack our quiver with the following essential competencies :

Inhouse design methodologies, checklists and templates

A library of essential design components like slow speed peripherals and small processing elements

Ability to convert digital processing algorithms to optimum HDL code

Understanding of internal bus protocols, peripheral protocols and audio/video processing elements

Analysis and implementation tool expertise ranging from simulators, synthesis, power analysis and optimization tools, Lint and CDC tools and DFT coverage analysis tools

Our top-class design talent, advanced tools and robust processes will deliver optimum outcomes for your next design project.

Digital Verification: Functionality, Performance, Power and beyond

With the complexity of digital designs of today, we understand that the verification process needs to employ a multi-pronged approach to cover the vast verification state space. At Ignitarium we have done extensive work on the following:

Verification planning using detailed inhouse test templates and EDA tools like Vplanner

Partitioning verification execution between simulation, emulation, assertions and connectivity checkers like Jasper to achieve coverage goals within reduced timelines

Deep experience in System Verilog and UVM

If you have a complex design with stringent timelines and near impossible coverage goals, do give us a call.

Mixed Signal Verification: Home-brewed

Mixed Signal verification has for long lagged its more advanced digital cousin. We decided to do something about it and rolled our own methodology leveraging the strengths of System Verilog, UVM and classical analog. The salient features of this methodology include:

Automation of verification and checker mechanisms for the Analog to Digital interface

Establishing coverage goals for Analog signals

Bringing randomization to Analog signals

Leveraging assertions to check the interface

Capability to use either SV-real models or actual spice models for Analog blocks

Speeding up the overall AMS verification time

Our Mixed Signal verification methodology has seen live deployment in several production proven silicon programs. Talk to us to know more.

We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. By clicking "Accept All", you consent to the use of ALL the cookies. However, you may visit "Cookie Settings" to provide a controlled consent.